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Features
* * * * * * * * * * * * * * * * * * *
AVR(R) Microcontroller-based Function Controller Fully Programmable USB Low-/Full-speed Function with Five Endpoints High Performance and Low Power 1.5/12/24 MIPs AVR RISC Microcontroller 120 Powerful Instructions - Most with 83 ns Execution Cycle Times 24 KB Masked ROM Program Memory 1 KB Internal SRAM 32 x 8 General-purpose Working Registers 19 Programmable I/O Port Pins 12 Channels 10-bit A-to-D Converter Programmable SPI Serial Interface One 8-bit Timer Counter with Separate Pre-scaler One 16-bit Timer Counter with Separate Pre-scaler and Two PWMs External and Internal Interrupt Sources Programmable Watchdog Timer Low Power Idle and Power-down Modes 6 MHz Crystal Oscillator with PLL 5V Operation with On-chip 3.3V Regulators 48-lead LQFP Package Binary-compatible with the AT43USB355
Full-speed/ Low-speed USB Microcontroller with ADC and PWM AT43USB351M Summary
Description
The Atmel AT43USB351M is a USB AVR-based microcontroller that is configurable as a low-speed or full-speed USB device. Its program memory is a 24-Kbyte mask programmable ROM and its data memory is 1-Kbyte SRAM. The on-chip peripherals consists of 19 general-purpose I/O ports, two timer-counters, SPI serial interface, a PWM and a 10-bit AD converter with 12 input channels. The MCU of the AT43USB351M is a high performance 8-bit AVR RISC that operates at a clock frequency of 1.5 MHz, 12 MHz or 24 MHz. The A-to-D converter has a minimum conversion time of 12 s that together with the 12 input channel should cover even the most demanding game controllers such as gamepads, joysticks and racing wheels. The two PWM outputs can be programmed for 8-, 9- or 10-bit resolution for applications requiring force feedback. The 19 general-purpose programmable I/O pins provide generous inputs for the various buttons and switches and LED indicators that are being used in increasing numbers in today's game controllers. The USB function has one control endpoint and four additional programmable endpoints, each with their own FIFOs. Two of the endpoints have a 64-byte FIFO each, while the other two have 8-byte FIFOs. The USB hardware supports the physical and link layers of the USB protocol while the transaction layer function must be implemented in the MCU's fir mware. The AVR architecture was developed to be programmed in C efficiently and without loss in performance. The AT43USB351M is binary-compatible with the AT43USB355. Program development and debugging for the AT43USB351M uses the AT43DK355 and all its tools and libraries.
Rev. 3302BS-USB-09/02
1
Pin Configuration
Figure 1. AT43USB351M 48-lead LQFP
CEXTA VCCA VSSA ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 26 ADC7 25 24 23 22 21 20 2XN 36
35
34
33
32
31
30
29
28
CEXT2 VCC2 VSS2 PD6 PD5 XTAL1 XTAL2 LFT PD4 PD3 PD2 PD1
37 38 39 40 41 42 43 44 45 46 47 48 10 11 1 12 2 3 4 5 6 7 8 9
27
ADC8 ADC9 ADC10 ADC11 TEST RESETN PA0 PA1 PA2 PA3 PA4 PA5
AT43USB351M-AC
19 18 17 16 15 14 13
PD0
DM
DP
PB7
PB6
PB5
PB4
PA7
VCC1
Figure 2. Low-/Full-speed USB Microcontroller with ADC and PWM
PA[0:7] DP0 USB DM0 PD[0:6] GPIO PB[4:7]
XTAL1 OSC + PLL XTAL2 LFT AVR TIMER/ COUNTER ADC ADC[0:11]
CEXT1
VSS1
PA6
VCC[1,2,A] SPI RSTN TEST ROM & SRAM VSS[1,2,A] VOLTAGE REGULATORS CEXT[1,2,A]
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Pin Assignment
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Signal PD0 DP DM CEXT1 VCC1 VSS1 PB7 PB6 PB5 PB4 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RESETN TEST ADC11 ADC10 ADC9 ADC8 Type Bi-directional Bi-directional Bi-directional Power Supply/Ground Power Supply/Ground Power Supply/Ground Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Input Input Input Input Input Input Pin# 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Signal ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 VCCA CEXTA VSSA 2XN CEXT2 VCC2 VSS2 PD6 PD5 XTAL1 XTAL2 LFT PD4 PD3 PD2 PD1 Type Input Input Input Input Input Input Input Input Power Supply/Ground Power Supply/Ground Power Supply/Ground Input Power Supply/Ground Power Supply/Ground Power Supply/Ground Bi-directional Bi-directional Input Output Output Bi-directional Bi-directional Bi-directional Bi-directional
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3302BS-USB-09/02
Signal Description
Name VCC1, 2 VCCA VSS1, 2 VSSA CEXT1,2 CEXT XTAL1 XTAL2 LFT Type Power Supply/Ground Power Supply/Ground Power Supply/Ground Power Supply/Ground Power Supply/Ground Power Supply/Ground Input Output Input Function 5V Digital Power Supply 5V Power Supply for the ADC Digital Ground Ground for the ADC External Capacitors for Power Supplies - High quality 2.2 F capacitors must be connected to V331 and V332 for proper operation of the chip. External Capacitor for Analog Power Supply - A high quality 0.33 F capacitor must be connected to V33A for proper operation of the chip. Oscillator Input - Input to the inverting oscillator amplifier. Oscillator Output - Output of the inverting oscillator amplifier. PLL Filter - For proper operation of the PLL, this pin should be connected through a 0.01 F capacitor in parallel with a 100 resistor in series with a 0.1 F capacitor to ground (VSS). Both capacitors must be high quality ceramic. Upstream Plus USB I/O - This pin should be connected to CEXT1 through an external 1.5 k. Upstream Minus USB I/O Port A[0:7] - Bi-directional 8-bit I/O port with 2 mA drive strength and a programmable pull-up resistor. Port B[4:7] - Bi-directional 8-bit I/O port with 2 mA drive strength and a programmable pull-up resistor. PB[4:7] have dual functions as shown below: Port Pin PB4 PB5 PB6 PB7 PD[0:6] Bi-directional Alternate Function SSN, SPI Slave Port Select or SCL, I2C Serial Bus Clock MOSI, SPI Slave Port Select Input MISO, SPI Master Data In, Slave Data Out SCK, SPI Master Clock Out, Slave Clock In
DPO DMO PA[0:7] PB[4:7]
Bi-directional Bi-directional Bi-directional Bi-directional
Port D[0:6] - Bi-directional I/O ports with 2 mA drive strength and a programmable pull-up resistor. PortD[2:6] have dual functions as shown below: Port Pin PD2 PD4 PD3 PD5 PD6 Alternate Function INT0, External Interrupt 0 ICP, Timer/Counter, Input Capture INT1, External Interrupt 1 OC1A Timer/Counter1 Output Compare A OC1B Timer/Counter1 Output Compare B
ADC[0:11] TEST RESETN
Input Input Input
ADC Input[0:11] - 12-bit input pins for the ADC. Test Pin - This pin should be tied to ground. Reset - Active Low.
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AT43USB351M
Figure 3. The AT43USB351M Enhanced RISC Architecture
12K x 16 Program Memory
Program Counter
Status and Control
Interrupt Unit
Instruction Register
32 x 8 General-purpose Registers
8-bit Timer/Counter
16-bit Timer/Counter
ALU Instruction Decoder Watchdog Timer
Control Lines
1024 x 8 SRAM SPI Unit
19 GPIO Lines ADC
USB Function
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3302BS-USB-09/02
Architectural Overview
The AT43USB351M is binary-compatible with the AT43USB355 compound device. Firmware developed for the AT43USB355 will run on the AT43USB351M. The peripherals and features of the AT43USB351M microcontroller are similar to those of the AT90S8515, with the exception of the following modifications: * * * * * * No EEPROM No External Data Memory Accesses No UART Idle Mode not Supported USB Function On-chip ADC
The embedded USB hardware of the AT43USB351M is a USB function with an 8-byte control endpoint and four additional programmable endpoints with separate FIFOs. Two of the FIFOs are 64 bytes deep and the other two are 8 bytes deep. Depending on the USB speed and the state of 2XN input signal, device pin 36, the MCU runs at 1.5 MHz, 12 MHz or 24 MHz. The clock that operates the MCU is generated by the USB hardware. While at 12 MHz, the nominal and average period of the clock is 83.3 ns, it may have single cycles that deviate by 20.8 ns during a phase adjustment by the SIE's clock/data separator of the USB hardware. Similarly at 1.5 MHz, the MCU clock runs 8 times slower and at 24 MHz, two times faster than the 12 MHz mode. The clock frequencies of the various modules of the AT43USB351M is summarized in the following table:
USB Mode Full Speed Full Speed Low Speed Low Speed
2XN Pin 0 1 0 1
MCU Clock 24 MHz 12 MHz 24 MHz 1.5 MHz
Timer/Counter Clock 12 MHz 12 MHz 12 MHz 1.5 MHz
ADC Clock 1 MHz 1 MHz 1 MHz 1 MHz
SPI Clock 24 MHz 12 MHz 24 MHz 1.5 MHz
WDT Clock 1 MHz 1 MHz 1 MHz 1 MHz
The microcontroller shares most of the control and status registers of the megaAVR Microcontroller Family. The registers for managing the USB operations are mapped into its SRAM space. Please refer to the Atmel AVR manual for more information. The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for look-up tables in program memory. These added function registers are the 16-bit X-, Y- and Z-registers. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 3 on page 5 shows the AT43USB351M AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowest Data Space addresses ($00 - $1 F), allowing them to be accessed as though they were ordinary memory locations.
6
AT43USB351M
3302BS-USB-09/02
AT43USB351M
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is a downloadable SRAM or a mask programmed ROM. With the relative jump and call instructions, the whole 24K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently, the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the Stack Pointer (SP) in the reset routine (before subroutines or interrupts are executed). The 10-bit SP is read/write accessible in the I/O space. The 1-Kbyte data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
Development Support
The AT43USB351M uses the same program and development tools as the AT43USB355 and other Atmel AVR microcontrollers, including: C compilers, macro assemblers, program debuggers/simulators and in-circuit emulators. The AT43DK355 development kit is also available, including firmware source code for the most common USB applications.
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3302BS-USB-09/02
Ordering Information
Program Memory Mask ROM Ordering Code AT43USB351M-AC Package 48 LQFP Operation Range Commercial (0C to 70C)
Package Type 48AA 48-lead, 7 x 7 mm Body Size, Low Profile Plastic Quad Flat Package (LQFP)
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Package Information
48AA - LQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 1.35 8.75 6.90 8.75 6.90 0.17 0.09 0.45 NOM - - 1.40 9.00 7.00 9.00 7.00 - - - 0.50 TYP MAX 1.60 0.15 1.45 9.25 7.10 9.25 7.10 0.27 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation BBC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 48AA, 48-lead, 7 x 7 mm Body Size, 1.4 mm Body Thickness, 0.5 mm Lead Pitch, Low Profile Plastic Quad Flat Package (LQFP) DRAWING NO. 48AA REV. C
R
9
3302BS-USB-09/02
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3302BS-USB-09/02 xM

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